Chip modules are small chips with clearly defined functions that can be combined with other chip modules into a single package or system. The dense interconnections between chip modules ensure fast, high-bandwidth electrical connections. This article discusses both interlayer technology and three-dimensional integration methods aimed at reducing interconnection spacing to below 1 micrometer.
This is the first part of a two-part series specifically discussing chip set components, which covers the latest developments in interconnection technology.
Chip Module Technology Beyond Hype
MIT Technology Review has listed chip module technology as one of the top 10 breakthrough technologies of 2024, and chip module technology has attracted widespread attention in the semiconductor industry. Chip module technology refers to small, dedicated-function chip modules, such as CPUs or GPUs, which can be mixed and matched to form a complete system. This Lego-like approach gives manufacturers flexibility to design new chips at a lower cost, and improves efficiency and performance. One way to achieve optimization in chip module technology is through strategic customization of technology. For example, IO and bus chip modules use reliable traditional process nodes, while computing chip modules adopt cutting-edge technology to achieve the highest performance. Memory chip modules adopt emerging storage technologies to ensure adaptation to diverse semiconductor needs. In addition, chip module-based designs accelerate the development process, as outdated chip modules can be updated more easily and frequently. Moreover, chip modules typically have a high yield because they are usually smaller in size and simpler in design, and can use known good die after pre-bonding testing, and can rely on repair strategies to fix defective interconnections.
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Deconstructing Large Monolithic SoCsThe modular design of chips has addressed the slowdown of Moore's Law, which has driven the semiconductor industry for decades. To ensure that the number of integrated circuit components doubles every two years, chip manufacturers have explored methods to make transistors smaller and integrate more components on chips, leading to the design of large monolithic systems on a chip (SoC). Mobile phones are proof of the success of monolithic design, integrating mathematical functions, display, wireless communication, audio, etc., into a chip with an area of only 100 square millimeters. However, further reduction also makes the performance advantages relatively more expensive. Therefore, the idea of breaking down large complex SoCs into smaller chip modules and connecting them to build specific application systems has emerged.
The automotive industry is an ideal candidate for adopting chip modular technology, providing a flexible electronic architecture with basic functional chip modules, adding specific components, including chip modules for autonomous driving, sensor fusion, and other electronic functions. The modular approach shortens the time to market, and can replace or update chip modules during the production line life cycle, compared to the lengthy process involved in upgrading a single monolithic SoC. In addition, car sales, especially considering specific models and types, are usually smaller than mobile phone sales. Therefore, redesigning a monolithic SoC for each model (part) will lead to high engineering costs. Finally, chip modularization also provides flexibility to help car manufacturers meet the demand for chips that have proven reliability and safety in other models.
With the rapid growth of the chip module market, it is expected that this modular design will appear in more application fields, such as imaging devices, display devices, storage devices, and quantum computing.
Figure 1: The chip modular system combines independent chips from different suppliers and technology nodes, instead of integrating all functions into a single system on a chip.
Connecting these "building blocks"
Whether chip modularization can keep up with Moore's Law largely depends on how to place chip modules closely within a package to ensure fast, high-bandwidth electrical connections between them, just like the functions in a monolithic SoC.
In three-dimensional system integration, there are two main industry directions: 2.5D chip module integration connects chips side by side through a common substrate (also known as an interposer), while 3D-SoC stacks chip modules vertically.2.5D Intermediate Layer Technology
In 2.5D integration, chip modules are connected through a common substrate such as silicon, organic polymer, glass, or laminated material. Imec is currently focusing on the research and optimization of silicon and organic substrates. Although the silicon intermediate layer has become a mature technology in high-performance applications, with excellent fine-pitch and good thermoelectric performance, its cost and complexity are also relatively high. Therefore, organic matrices are being studied and optimized as alternative solutions.
Early chip module integration mainly focused on establishing connections between chip modules using a silicon intermediate layer substrate. This involves placing two separate chip modules very close to each other on a common intermediate layer (with a distance of less than 50 micrometers), where the intermediate layer has micrometer-level wiring to establish connections. The silicon intermediate layer utilizes traditional BEOL copper/oxide pit filling process technology to achieve micrometer and sub-micrometer connection pitches, with a very high yield rate.
Although this is still an effective method, alternative technologies are attracting interest as they may offer more cost-effective solutions. One option provided by Imec is the silicon "bridge," which is a small silicon intermediate layer that only connects the chip modules at their edges.
Another alternative is the ultra-fine redistribution layer (RDL) interconnection technology, which replaces silicon with an organic polymer and embeds a layer of copper wires for connecting chip modules. Imec is currently optimizing this technology, striving to achieve an interconnection density similar to silicon and improving its compatibility with silicon. In terms of interconnection pitch, the intermediate layer still leads with sub-micrometer spacing; Imec is targeting a 2-micrometer RDL pitch and plans to further reduce it to the sub-micrometer level in the future.
In addition to exploring alternative technologies to silicon intermediate layers, Imec is also researching how to make the intermediate layer a more valuable component by adding additional functions. For example, an intermediate layer can add extra decoupling capacitors to protect chip modules from noise and power supply anomalies.
Three-Dimensional Chip-on-Chip Systems: Hybrid Bonding Achieves Sub-Micrometer Pitch
Certain applications, such as high-performance computing, may require higher performance, smaller size, or a higher level of system integration, and thus prefer a fully three-dimensional approach. Instead of establishing lateral connections, chip modules can be stacked to form a three-dimensional chip-on-chip system (3D-SoC). This method involves co-designing chip modules and making them operate as if they were on the same chip. Chip-to-chip hybrid bonding is the key technology for achieving sub-micrometer interconnection density levels in 3D chip-on-chip systems. It involves connecting two silicon chip modules together using a low expansion coefficient. A key component of this process is the dielectric layer, which flattens and activates the surfaces of the stacked layers for effective bonding and provides electrical insulation between different chip modules in the stack. Imec's proprietary method of using SiCN as the bonding dielectric layer reduces the interconnection pitch to 700 nanometers. Its technology roadmap even predicts pitches of 400 nanometers and 200 nanometers.Comparison of Microbumps and Hybrid Bonding
In 2.5D technology, chip modules are placed on an interposer layer through small solder bumps, achieving electrical and mechanical connections. The finer the pitch between these microbumps, the higher the connection speed and stability. The industry-standard pitch for microbumps typically ranges from 50 micrometers to 30 micrometers. Imec is researching how to reduce this pitch to 10 micrometers or even 5 micrometers.
Compared to the microbumps used in 2.5D, hybrid bonding in 3D stacking can achieve significantly smaller pitches. So, can hybrid bonding be used everywhere? Indeed, in chip-to-chip approaches (based on silicon), chip modules can be bonded to a silicon interposer, achieving pitches of a few micrometers. However, compared to the current best chip-to-chip placement accuracy of approximately 250 nanometers, cutting-edge chip-to-chip bonding can achieve a stacking accuracy of 100 nanometers. It is expected that improvements in bonding equipment and related processes will further reduce these figures by about 50%. However, hybrid bonding involves additional processing steps, such as surface activation and alignment, which may affect manufacturing costs.
Chip-to-chip bonding, chip-to-wafer bonding, and microbumps will trade off between cost, pitch, compatibility, and interoperability. In 2.5D, chip modules typically come from different suppliers and have already undergone a series of tests and processes. Since microbumps provide a standardized method without the need for surface preparation, they will be the preferred choice. Moreover, for organic RDL, microbumps remain the preferred method because organic polymers expand more when heated and cannot be fully planarized.
Summary and Reflection
As technology scaling becomes more complex and drives up design and processing costs, developing dedicated SoCs at the most advanced technology nodes becomes more challenging—think of the excessive models and types in the automotive industry. Separating functions and technology nodes into different chip modules has proven to be more cost-effective than manufacturing large chips in advanced process technologies, bringing advantages in space and performance.
Although the modular approach can address the complexity and cost issues of multi-chip packaging, this paradigm shift also brings specific technical challenges. Size is just one of the challenges. An important direction in chip module research is to make interconnections smaller or explore different concepts for integrating different components. When stacking chip modules, thermal issues and power transmission (addressed by new architectures such as backside power delivery networks) become crucial. Finally, further standardization work is needed to ensure compatibility and communication between different chip modules.*Declaration: This article is the original creation of the author. The content of the article represents the author's personal views. Our reposting is solely for the purpose of sharing and discussion, and does not represent our endorsement or agreement. If there are any objections, please contact the backend.
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