The memory market is on the cusp of a new "revolution" in DRAM technology.
Amidst the surge in AI applications, the demand for high-performance memory continues to soar, with DRAM represented by HBM garnering immense popularity. Concurrently, to further meet market demands, memory manufacturers are poised and ready to usher in a new "revolution" in DRAM technology.
Smooth Development of 4F Square DRAM
Recently, Samsung Electronics Vice President, Liu Changzhi, announced that the progress of Samsung's next-generation DRAM technology is proceeding smoothly. In addition to the successful mass production of 1b DRAM, the development of 4F Square DRAM technology is also advancing well, with the initial samples of 4F Square DRAM expected to be developed by 2025.
Advertisement
It is reported that the early DRAM cell structure was an 8F square grid, and the DRAM currently in commercial use mainly adopts a 6F square grid. Compared to these two technologies, the 4F square grid utilizes a vertical channel transistor (VCT) structure, which can reduce the chip area by 30%.
Due to the reduction in cell area, the DRAM density and performance have been enhanced. Therefore, driven by applications such as AI, the 4F Square technology is gradually gaining favor with major storage manufacturers.Previously, Samsung stated that many companies are striving to transition their technologies to 4F Square VCT DRAM, although some challenges still need to be overcome, including the development of new materials such as oxide channel materials and ferroelectrics.
Industry insiders believe that the first batch of 4F Square DRAM samples launched by Samsung in 2025 may be used for internal release. Another semiconductor manufacturer, Tokyo Electron, estimates that DRAM using VCT and 4F Square technology will emerge between 2027 and 2028.
In addition, Samsung plans to apply Hybrid Bonding technology to support the production of 4F Square DRAM. Hybrid Bonding is the next-generation packaging technology, which refers to increasing cell density by vertically stacking chips to improve performance, and this will also have an impact on the development of HBM4 and 3D DRAM.
HBM4 is on the horizon.
In the era of AI, HBM, especially HBM3e, is gaining popularity in the memory market, with competition among the three major DRAM manufacturers becoming increasingly fierce. A new round of competition is underway, with the focus on the next-generation HBM4 technology.
In April this year, SK Hynix announced a collaboration with TSMC to develop HBM4. It is reported that the two companies will first improve the performance of the Base Die at the bottom of the HBM package. In order to focus on the development of the next-generation HBM4 technology, Samsung has established a new "HBM Development Team."
In July, Choi Sang-hee, head of the new business planning team of Samsung Electronics' memory division, revealed that the company is developing a high-capacity HBM4 memory with a single stack of up to 48GB, which is expected to go into production next year. It is reported that Samsung plans to use 4nm advanced process technology to produce HBM4 logic chips. Micron plans to launch HBM4 between 2025 and 2027, and transition to HBM4E in 2028.
In addition to manufacturing processes, DRAM manufacturers are also actively exploring hybrid bonding technology for future HBM products. Compared with existing bonding processes, hybrid bonding eliminates the need for bumps between DRAM memory layers, instead directly connecting the upper and lower layers, copper to copper. This significantly improves signal transmission speed and better meets the high bandwidth requirements of AI computing.
In April this year, Samsung successfully manufactured a 16-layer stacked HBM3 memory based on hybrid bonding technology, and the memory sample operates normally. In the future, this 16-layer stacked hybrid bonding technology will be used for mass production of HBM4. SK Hynix plans to apply hybrid bonding to HBM production before 2026. Micron is also developing HBM4 and considering related technologies, including hybrid bonding, all of which are currently under research.The Momentum of 3D DRAM Development is Strong
3D DRAM (Three-Dimensional Dynamic Random Access Memory) is a new type of DRAM technology with a novel storage cell structure. Unlike traditional DRAM with horizontally placed storage cells, 3D DRAM stacks storage cells vertically, significantly increasing the storage capacity per unit area and improving efficiency. This makes it a key development direction for the next generation of DRAM.
In the memory market, 3D NAND Flash has been commercially applied, while 3D DRAM technology is still under development. However, with the rapid development of applications such as AI and big data, the demand for high-capacity and high-performance memory will increase significantly, and 3D DRAM is expected to become a mainstream product in the memory market.
HBM technology has paved the way for the 3D evolution of DRAM, allowing DRAM to transition from traditional 2D to 3D. However, the current HBM cannot be considered a true 3D DRAM technology. Samsung's 4F Square VCT DRAM is closer to the concept of 3D DRAM, but it is not the only direction or goal for 3D DRAM. Memory manufacturers have more ideas and creativity in the field of 3D DRAM.
Samsung plans to commercialize 3D DRAM by 2030. In 2024, Samsung demonstrated two 3D DRAM technologies, including VCT and stacked DRAM. Samsung first introduced VCT technology, and then upgraded to stacked DRAM by stacking multiple VCTs together, continuously improving the capacity and performance of DRAM.
Samsung stated that stacked DRAM can fully utilize the Z-axis space, accommodating more storage cells in a smaller area, with a single chip capacity exceeding 100Gb. In May of this year, Samsung pointed out that it has successfully manufactured a 16-layer 3D DRAM together with other companies, but emphasized that it is not yet ready for mass production. 3D DRAM is expected to be produced using wafer-to-wafer hybrid bonding technology, and the BSPDN (Backside Power Delivery Network) technology is also being considered.
Micron has submitted 3D DRAM patent applications different from Samsung, aiming to change the shape of transistors and capacitors without placing cells.
SK Hynix's manufacturing yield of 5-layer stacked 3D DRAM has reached 56.1%. This means that out of about 1,000 3D DRAMs produced on a test wafer, about 561 viable devices were manufactured. The experimental 3D DRAM exhibits characteristics similar to the currently used 2D DRAM, which is the first time SK Hynix has disclosed specific numbers and characteristics of its 3D DRAM development.
In addition, the American company NEO Semiconductor is also committed to the research and development of 3D DRAM. Last year, NEO Semiconductor announced the launch of the world's first 3D DRAM prototype product: 3D X-DRAM. This technology is similar to 3D NAND Flash, that is, increasing memory capacity by stacking layers, and has characteristics such as high yield, low cost, and high density.NEO Semiconductor plans to launch its first-generation 3D X-DRAM in 2025, with a stack of 230 layers and a core capacity of 128Gb, which is several times higher than the 16Gb capacity of 2D DRAM.
*Statement: This article is the original creation of the author. The content of the article represents the author's personal views. Our reposting is solely for sharing and discussion, and does not represent our endorsement or agreement. If there are any objections, please contact the backend.
Leave a Reply