Recently, experts have called for the industry to unify packaging and testing technology standards as soon as possible, especially for advanced packaging.
SEMI Japan Office President Jim Hamajima stated that the chip industry needs more international standards for the backend production process to enable wafer factories such as Intel and TSMC to improve production capacity more effectively. At present, companies like TSMC and Intel are building their own advanced chip packaging technology systems and ecosystems, all using different standards, which results in low production efficiency.
Jim Hamajima said that the backend processes, including chip packaging and testing, are more "fragmented" than the front-end processes of chip manufacturing (such as lithography), which widely use standards set by SEMI. He believes that as companies pursue more powerful chips, this may affect the industry's profit margins.
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High Threshold for Chip Manufacturing, Easy Standardization
Chip manufacturing is the segment with the highest threshold in the semiconductor industry, with high investment and few players. Currently, in the field of advanced process chip manufacturing, only TSMC, Samsung, and Intel remain.
The chip manufacturing process requires more than 2000 steps and can be divided into 8 major steps, including:
Lithography, which is the process of transferring the pattern on the photomask to the wafer below the photoresist through exposure and development procedures. Lithography mainly includes photoresist coating, baking, mask alignment, exposure, and development processes. Exposure methods include: ultraviolet, extreme ultraviolet, X-rays, electron beams, etc.
Etching, which is the technology of removing materials using chemical reactions or physical impact. Dry etching utilizes the physical effect produced by plasma hitting the wafer surface, or the chemical reaction between plasma and the atoms on the wafer surface, or a combination of both. Wet etching uses chemical solutions to achieve etching through chemical reactions.Chemical Vapor Deposition (CVD).
Physical Vapor Deposition (PVD).
Ion Implantation.
Chemical Mechanical Polishing (CMP).
Cleaning.
Wafer Dicing (Die Saw).
In the more than 2000 process steps, there lies the wisdom, core technology, and substantial financial strength of the wafer factory. The technology content is very high, and it requires long-term accumulation. It is not the case that by purchasing advanced equipment, one can produce qualified chips. Of course, advanced equipment is also very important; after all, even a skilled cook cannot make a meal without rice.
Due to the huge investment and high technological content, especially in more advanced process technologies, the high barriers to entry in terms of capital and technology make the number of players relatively small. Moreover, as advanced processes develop to 3nm and 2nm, the barriers become even higher, and the difficulty of moving forward and evolving is extremely high, making it challenging even for the few players involved. Under these circumstances, it is difficult to achieve a situation where a hundred flowers bloom together, making it relatively easy to unify standards and use them for a longer period.
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The Battle for New Packaging and Testing StandardsPackaging and testing is the final stage in chip production. In most cases, the technical content and implementation difficulty of packaging and testing are lower than those of front-end chip manufacturing. However, chip packaging also has standards, which are relatively numerous and change more rapidly than the standards for front-end chip manufacturing. Especially as chips are moving towards high integration, small feature sizes, and high I/O, higher requirements are being placed on packaging technology. With the emergence and development of SiP and advanced packaging technologies, it is necessary to redefine chip packaging and testing. At the same time, due to the bottlenecks in technology and process development faced by front-end chip manufacturing (such as the failure of Moore's Law), back-end packaging has become the key to victory in the eyes of wafer giants. In recent years, major wafer factories have been actively investing in the research and development of advanced packaging technologies.
In summary, the front-end chip manufacturing process is difficult to break through, while the back-end packaging is relatively easier. These two factors together have driven the emergence of new packaging technologies and standards.
Globally, the market share of advanced packaging reached 47.2% in 2022, and the growth rate of the advanced packaging market has exceeded that of traditional packaging. It is expected that by 2026, the market share of advanced packaging will increase to 50.2%. This growth is mainly due to the strong demand in the fields of AI and high-performance computing, which have a huge demand for high-integration, high-performance, and low-power chips.
At present, advanced packaging technology is still mainly based on flip-chip packaging, and the growth rate of 3D stacking and embedded substrate packaging (ED) is also very fast. In addition, other advanced packaging technologies, such as fan-out packaging and wafer-level packaging (WLCSP), also occupy an important position in the market. These packaging technologies have significant advantages in improving chip performance and reducing packaging size, and are widely used in smartphones and other mobile devices.
At present, the most popular application of advanced packaging is HBM memory. HBM achieves high-speed data transmission through the stacking of logic chips and multi-layer DRAM, with each layer connected by through-silicon vias (TSV) and micro-bumps, breaking through the bandwidth bottleneck and becoming the preferred choice for AI training chips. The internal DRAM stacking of HBM belongs to 3D packaging, while the combination of HBM with other parts is packaged on a silicon interposer, which belongs to 2.5D packaging.
In the high-tech industry, first-class companies set standards, and second-class companies implement standards. The semiconductor industry is a typical representative.
In terms of advanced chip packaging technology, large companies not only comply with the industry's implementation standards but also surpass these standards to form their own unique standards and processes. They are actively formulating a series of specifications and requirements, including process flow, equipment parameters, material selection, and quality control. This can reflect the technical level and innovation ability of chip manufacturing companies, which is beneficial for winning customers and enhancing competitiveness.
It is also important to note that, unlike traditional packaging and testing processes, the key processes of advanced packaging need to be completed on the front-end chip manufacturing platform, which is an extension of the front-end process. This is obviously an innate advantage for wafer giants such as TSMC, Samsung, and Intel, so it is more natural for them to develop advanced packaging processes.
At present, in terms of the commercialization of advanced packaging technology, TSMC started early and has the greatest market influence.
At present, the popular HBM memory mainly uses TSMC's CoWoS packaging technology. CoWoS is a 2.5D packaging technology developed by TSMC in 2012, which can be divided into two steps: CoW (chip on wafer) and oS (on substrate). CoW is the packaging of the computing core, I/O die, HBM, and other bare chips on the silicon interposer, and then the CoW bare chips are packaged on the substrate, which is the oS process. CoWoS can save space, achieve the high interconnection density and short-distance connection required by HBM; it can also package chips of different processes together, meeting the needs of AI, GPU, and other accelerated computing while controlling costs.According to Omdia statistics, in the third quarter of 2023, Nvidia sold nearly 500,000 A100 and H100 chips, benefiting from the demand for artificial intelligence and high-performance computing, Nvidia achieved revenue of $14.5 billion in data center hardware for that quarter. In addition to Nvidia, AMD's latest AI GPU product, MI300, will also adopt TSMC's CoWoS (2.5D) and SolC (3D) packaging technologies. The huge demand has led to a shortage of CoWoS production capacity.
In addition to CoWoS, TSMC is also developing new packaging technologies. It is reported that the leading wafer foundry has established a dedicated team to enter the FOPLP (Fan-out Panel Level Package) packaging technology that has been developed by professional packaging and testing factories (OSATs) for many years. The FOPLP developed by TSMC can be regarded as a rectangular CoWoS package, which is currently mainly aimed at the AI GPU field led by Nvidia, with advantages such as lower unit cost and larger packaging size. In the future, it can further integrate other technologies on TSMC's 3D Fabric platform, paving the way for 2.5D/3D advanced packaging solutions to serve high-end product applications.
Seeing TSMC making a splash in the advanced packaging market, Samsung and Intel need to step up their efforts.
Samsung and Intel are also aware of the issue and have invested in the development of new generations of advanced packaging technologies.
At present, Samsung's self-developed advanced packaging technologies and services include I-Cube (2.5D) and X-Cube (3D). For applications requiring low-power memory such as smartphones or wearable devices, Samsung has provided panel-level fan-out packaging and wafer-level fan-out packaging platforms.
Samsung's I-Cube packaging technology has multiple versions, among which, I-Cube S is a heterogeneous technology that places a logic chip and a set of HBM bare chips horizontally on a silicon interposer, achieving high computing power, high bandwidth data transmission, and low latency. I-Cube E technology uses a silicon embedded structure, featuring a large size PLP (Panel Level Packaging Technology), a RDL interposer with no silicon through-hole structure, etc. H-Cube is a hybrid substrate structure that combines ABF substrate and HDI (High Density Interconnect) technology, which can achieve a larger packaging size in the I-Cube 2.5D packaging.
Intel is promoting its Embedded Multi-die Interconnect Bridge (EMIB) 2.5D packaging technology. The main advantages of EMIB are its simple structure and low signal interference. With this technology, there is no need to manufacture a silicon interposer covering the entire chip and a large number of silicon through-holes on the silicon interposer during the packaging process. Interconnecting between bare chips can be achieved using a smaller silicon bridge. Compared with ordinary packaging technology, the connection from chip I/O to packaging pins has not changed, and there is no need to route through silicon through-holes or silicon interposers. This architecture and process can not only reduce the transmission delay between different bare chips but also reduce signal transmission interference.
Due to Samsung and Intel's advanced process (below 5nm) market influence and commercialization level are obviously weaker than TSMC, in this case, the advanced packaging technology that is highly dependent on front-end chip manufacturing processes and platforms is difficult to break through, and the ability to make money is limited.
As the market share of advanced packaging is increasing, wafer factories have an innate development advantage, which makes traditional OSAT packaging and testing factories somewhat awkward, and their development pace is not as smooth as TSMC. TSMC's strong position in the field of advanced packaging has prompted it to invest more resources in advanced packaging technologies and services to further consolidate its market position. This may result in fewer opportunities for OSAT companies.
Traditional OSAT giants such as ASE Technology and Amkor Technology will not sit idly by.In the broad sense of advanced packaging, traditional OSATs still hold a significant market share. According to Yole, in 2022, the advanced packaging market saw OSATs with a market share of 65.1%, IDMs with 22.6%, and foundries with 12.3%. Among them, ASE Technology had the highest proportion at 25.0%, Amkor with 12.4%, TSMC with 12.3%, Samsung with 9.4%, and Intel with 6.7%. However, IDMs and foundries focus on high-end 3D packaging, while OSATs are generally more traditional, focusing on mid to low-end flip-chip and wafer-level packaging. In the current rapid development of AI processors and HBM memory, the trend of development is on the side of IDMs and foundries. To keep up with the development trend, OSAT packaging and testing factories must invest more resources in high-end packaging processes and services.
Taking ASE Technology, a leader in packaging and testing, as an example, it is developing new packaging technologies, such as Fan-Out Chip on Substrate (FOCoS). FOCoS is a fan-out packaging flip-chip technology installed on a high-pin-count Ball Grid Array (BGA) substrate. Fan-out packaging has a redistribution layer (RDL) that allows for the construction of shorter chip-to-chip (D2D) interconnections between multiple chips, with flip-chip mounted on the BGA substrate. FOCoS-CF consists of two ASIC chips facing down, directly connected to the RDL through Cu vias, with no microbumps between the silicon wafer and the fan-out RDL. In FOCoS-CL, the ASIC chip and two HBMs are connected through RDL and Cu microbumps. FOCoS-Bridge uses a silicon bridge chip embedded in the fan-out RDL layer to connect the ASIC and HBM.
To keep up with the advanced packaging trend, ASE Technology's CFO, Dong Hongsi, pointed out that in response to the current market demand, the capital expenditure for 2024 will be doubled on the basis of $1.5 billion in 2023. Among them, packaging expenditure accounts for about 53%, and testing expenditure accounts for about 38%. Advanced packaging is the focus of investment.
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Chinese mainland packaging and testing factories are catching up
In the current vigorous development of advanced packaging, Chinese mainland enterprises are also developing related technologies to keep up with the pace of industrial development.
JCET is a leading enterprise in the packaging industry of the Chinese mainland. The company is developing XDFOI technology (2.5D ultra-high-density fan-out packaging). This packaging technology can integrate chips with different functions within the system packaging, especially suitable for applications with high requirements for integration and computing power, such as FPGAs, CPUs, GPUs, and 5G network chips. XDFOI technology can not only improve integration but also enhance performance and power efficiency.
Tongfu Microelectronics' VISionS technology can achieve multi-layer wiring, high-density integration of Chiplet small chips with different processes and functions, providing wafer-level and substrate-level packaging solutions. The company has achieved mass production of stacked NAND Flash and LPDDR packaging, and its 3D storage packaging technology is at the leading level in China.
Hua Tian Technology has launched the 3D Matrix technology, integrating advanced packaging technologies such as silicon through-hole, eSiFo (Fan-out), and 3D SIP. Fan-out technology significantly improves packaging density and performance by etching trenches on the substrate, placing chips in the trenches, and then re-wiring and packaging.
In addition, enterprises such as Huawei, BYD Semiconductor, and Alibaba play an important role in packaging design, application, and market promotion in various links of the industry chain.
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