As the advantages of planar scaling diminish, the competition in the three-dimensional domain and new technologies in the foundry sector is intensifying.
The three leading-edge foundries—Intel, Samsung, and TSMC—have begun to fill in some key parts of their roadmaps, adding aggressive delivery dates for future generations of chip technology, and laying the groundwork for significant performance improvements and shortened delivery times for custom designs.
Unlike in the past, where there was a single industry roadmap determining how to advance to the next process node, today, the three largest foundries are increasingly forging their own paths. They are all moving in the same general direction, with 3D transistors and packaging, a range of supporting and extending technologies, and a larger, more diverse ecosystem. However, there are some key differences in their approaches, architectures, and third-party support.
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The roadmaps of these three players indicate that transistor scaling will continue at least to the 18/16/14 nm range, and at some point in the future, may shift from nanosheet and forksheet field-effect transistors (FETs) to complementary field-effect transistors (CFETs). The key driving factors are artificial intelligence/machine learning and the surge in data that needs to be processed. In most cases, these will involve processing arrays of components, often with a high level of redundancy and homogeneity to achieve higher yields.
In other cases, these designs may contain dozens or even hundreds of chips, some for specific data types and others for more general processing. These chips can be mounted on a substrate in a 2.5D configuration, a method favored in data centers because it simplifies the integration of high-bandwidth memory (HBM), and also promoted in mobile devices, where it includes additional functions such as image sensors, power supplies, and additional digital logic for non-critical functions. All three foundries are working on complete 3D-ICs. There will also be hybrid options available, where logic is stacked on logic and mounted on a substrate, but separated from other functions to minimize physical impacts such as heat—this heterogeneous configuration is referred to as 3.5D and 5.5D.
Rapid and large-scale customizationOne of the most significant changes is the acceleration of bringing designs specific to certain fields to the market at a faster pace than in the past. This may sound mundane, but for many cutting-edge chips, it is a necessity for competition, requiring a fundamental change in the way chips are designed, manufactured, and packaged. To make this plan work, it is necessary to combine standards, innovative connection schemes, and various engineering disciplines, which in the past had limited interaction or no interaction at all.
Sometimes referred to as "mass customization," it includes the usual trade-offs of power, performance, and area/cost (PPA/C), as well as rapid assembly options. This is the prospect of heterogeneous chip components, and from an extended perspective, it marks the next stage of Moore's Law. For more than a decade, the entire semiconductor ecosystem has been gradually laying the foundation for this transformation.
However, making heterogeneous chips (essentially enhanced IP from multiple suppliers and foundries) work together is both a necessary and formidable engineering challenge. The first step is to connect the chips in a consistent way to achieve predictable results, which is where foundries have put a lot of effort, especially in the areas of Universal Chiplet Interconnect Express (UCIe) and Bond over Wire (BoW) standards. Although this connectivity is a key requirement for the three, it is also one of the main areas of divergence.
Before fully integrated 3D-IC, Intel's current solution is to develop what industry insiders call chip "sockets." Instead of describing the features of each chip for the commercial market, the company defines specifications and interfaces so that chip suppliers can develop these function-limited microchips to meet these specifications. This solves a major obstacle in the commercial chip market. From data speed to heat and noise management, all components need to work together.
Intel's plan largely relies on its Embedded Multi-Chip Interconnect Bridge (EMIB), which was first introduced in 2014. Intel's Vice President of Technology Development, Lalitha Immaneni, said: "The really cool thing about the EMIB base is that you can add any number of chips." "We have no limit on the number of IPs that can be used in the design, and it does not increase the size of the intermediary layer, so it is cost-effective and process-independent. We provide a packaging assembly design kit, which is like a traditional assembly PDK. We provide them with design rules, reference processes, and tell them the allowed structures. It will also provide them with any accessories we need to bring into assembly."
According to the design, there can be multiple EMIBs in a package, supplemented by thermal interface materials (TIM) to dissipate heat that may be trapped inside the package. TIM is usually a pad designed to conduct heat away from the source, and as the amount of computing inside the package increases and the substrate becomes thinner to shorten the distance signals need to travel, TIM is becoming more common.
However, the thinner the substrate, the worse the heat dissipation effect, which can lead to thermal gradients related to workloads, making it difficult to predict. Eliminating these heat may require TIM, additional heat sinks, or even more exotic cooling methods, such as microfluidics.
TSMC and Samsung both provide bridges. Samsung embeds bridges in RDL (a method called 2.3D or I-Cube ETM) and uses them to connect subsystems to these bridges to extend the life of silicon wafers. Some integration work will be done in advance in well-known modules, rather than relying on the socket method.
Arm CEO Rene Haas said in a keynote speech at a recent Samsung foundry event: "Combining two, four, or eight CPUs into a system is something very mature customers know how to do. But if you want to build an SoC with 128 CPUs connected to a neural network, memory structure, interrupt controller interfaced with NPU, and off-chip bus connected to another chip, then this requires a lot of work. In the past year and a half, we have seen many people building these complex SoCs, hoping to get more from us."
Samsung has also been organizing a small chip supplier alliance for specific markets. The initial concept is that one company makes I/O chips, another company makes interconnects, and a third company makes logic. When this approach is proven to be feasible, other companies will join to provide more options for customers.TSMC has tried various different schemes, including RDL and non-RDL bridging, fan-out, 2.5D wafer-level chip (CoWoS), and System on Integrated Chip (SoIC), the latter being a 3D-IC concept where chips are packaged and stacked within a substrate using very short interconnects. In fact, TSMC has provided a process design kit for almost every application and has been actively creating assembly design kits for advanced packaging, including accompanying reference designs.
The challenge lies in the fact that foundry customers willing to invest in these complex packages increasingly want highly customized solutions. To achieve this, TSMC introduced a new language called 3Dblox, which is a top-down design scheme that integrates physical and connection structures, allowing assertions to be applied between the two. This sandbox approach allows customers to utilize any of their packaging methods—InFO, CoWoS, and SoIC. This is also crucial to TSMC's business model, as the company is the only pure foundry among the three—although Intel and Samsung have both distanced themselves from the foundry business in recent months.
"We started with the concept of modularity," said Jim Chang, TSMC's Vice President of Advanced Technology and Mask Engineering, during a presentation when 3Dblox was first introduced in 2023. "We can construct a complete 3D-IC stack with this language syntax and assertions."
Chang stated that the reason for this situation is the lack of consistency between physical and connection design tools. But he added that once this method is developed, it can also be reused in different designs for chips, as most of the features are already clearly defined, and the designs are modular.
Figure 1: TSMC's 3Dblox approach. Source: TSMC
Samsung subsequently launched its own system description language, 3DCODE, in December 2023. Both Samsung and TSMC claim that their languages are standards, but they are more like new foundry rule platforms because these languages are unlikely to be used outside of their own ecosystems. Intel's 2.5D approach does not require a new language because the rules are determined by the slot specification, which achieves some customization at the expense of shortening the time to market and providing a simpler method for chip developers.
Chip Challenges
Chips have obvious advantages. They can be independently designed at any reasonable process node, which is particularly important for analog functions. But how to combine the various parts and produce predictable results has always been a significant challenge. It turns out that DARPA's initial Lego-like architectural proposal is much more complex than initially imagined, requiring a vast ecosystem to make a lot of continuous efforts to achieve.Chipsets require precise synchronization to ensure that critical data can be processed, stored, and retrieved without delay. Otherwise, timing issues may arise, where a calculation is either delayed or out of sync with other calculations, leading to latency and potential deadlocks. In mission-critical or safety-critical applications, a loss of even one second can have serious consequences.
Simplifying the design process is an extremely complex task, especially for domain-specific designs, as there is no unified standard. The goal of these three foundries is to provide more options for companies developing high-performance, low-power chips. It is estimated that about 30% to 35% of all cutting-edge designs are currently handled by large system companies such as Google, Meta, Microsoft, and Tesla. The economics of cutting-edge chip and packaging designs have undergone significant changes, and the PPA/C formula and trade-offs have also changed significantly.
Chips developed for these system companies may not be commercially sold. Therefore, if they can achieve higher performance per watt, the design and manufacturing costs can be offset by reducing cooling power and increasing utilization—potentially reducing the number of servers. For chips sold to mobile devices and commercial servers, the situation is the exact opposite, where high development costs can be amortized through mass production. Custom designs in advanced packaging offer economic benefits to both, but for very different reasons.
Shrinking, Enlarging, and Shrinking Again
It is estimated that in these complex chiplet systems, there will be a variety of processors, some highly specialized and others more general-purpose. Due to limited power budgets, at least some of them may be developed on the most advanced process nodes. Advanced nodes still offer higher energy efficiency, allowing more transistors to be packaged into the same area to improve performance. This is crucial for AI/ML applications, as processing more data faster requires more multiply/accumulate operations in a highly parallel configuration. Smaller transistors provide higher energy efficiency, allowing more processing per square millimeter of silicon, but gate structures need to be changed to prevent leakage, which is why forksheet FETs and CFETs are on the horizon.
In short, process leadership still has value. Being the first to bring cutting-edge processes to market benefits companies, but this is just one piece of the larger puzzle. All three foundries have announced plans to move towards angstrom-scale processes. Intel plans to launch the 18A process this year, followed by the 14A process in a few years.
Figure 2: Intel's process roadmap. Source: Intel Foundry
Meanwhile, TSMC will add the A16 in 2027 (see Figure 3 below).Figure 3: TSMC's scaling roadmap into the Angstrom era. Source: TSMC
Samsung is set to enhance the resolution to 14 angstroms around 2027 using its SF1.4, apparently skipping over 18/16 angstroms. (See Figure 4)
Figure 4: Samsung's process expansion roadmap. Source: Samsung Foundry
From the perspective of process nodes, these three foundries are on the same track. However, progress is no longer solely related to process nodes. There is an increasing focus on the delay in specific domains and performance per watt, which is where the advantage of logic stacking in a true 3D-IC configuration lies, using hybrid bonding to connect chips to the substrate and each other. Moving electrons through wires on a planar chip is still the fastest (assuming the signal does not need to be transmitted from one end of the chip to the other), but stacking transistors on top of other transistors is the next best option, and in some cases, even better than a planar SoC, as some vertical signal paths may be shorter.
In a recent presentation, Taejoong Song, Vice President of Business Development at Samsung Foundry, showed a roadmap featuring logic stacking technology, with logic stacking technology mounted on the substrate, combining 2nm (SF2) chips with 4nm (SF4X) chips, both mounted on another substrate. This is essentially 3D-IC on a 2.5D package, which is the 3.5D or 5.5D concept mentioned earlier. Song stated that the foundry will start stacking SF1.4 on SF2P from 2027. The particularly appealing aspect of this approach is the possibility of heat dissipation. By separating logic from other functions, heat can be expelled from the stacked chips through the substrate or any of the five exposed faces.
Figure 5: Samsung's 3D-IC architecture for AI. Source: Samsung
Meanwhile, Intel will use its Foveros Direct 3D to stack logic on logic, either face-to-face or back-to-back. According to Intel's latest white paper, this method allows chips or wafers from different foundries to be connected, with the connection bandwidth determined by the copper via pitch. The paper points out that the first generation will use a 9µm copper pitch, while the second generation will use a 3µm pitch.Figure 6: Intel's Foveros Direct 3D. Source: Intel
"True 3D-IC with Foveros, and then also with hybrid bonding," said Intel's Immaneni. "You can't go the traditional design route, put everything together, then validate, and then find, 'Oops, I have a problem.' You can't do that anymore because you impact your time to market. So you really want to provide a sandbox to make it predictable. But even before I get into this detailed design environment, I want to run my mechanical/electrical/thermal analysis. I want to see the connectivity so that I don't have open circuits and short circuits. The burden of 3D-IC is more on the code design, not the execution."
Foveros allows active logic chips to be stacked on another active or passive chip, and connects all chips in the package with a base chip at a 36-micrometer pitch. By leveraging advanced sorting technology, Intel claims it can guarantee 99% known good chips and a 97% assembly post-test yield rate.
In the meantime, TSMC's CoWoS has been used by NVIDIA and AMD for their advanced packaging of AI chips. CoWoS is essentially a 2.5D approach that uses an interposer to connect the SoC and HBM memory through silicon vias. The company's plans for SoIC are more ambitious, encapsulating memory on logic along with other elements such as sensors in a 3D-IC at the front end of the production line. This can significantly reduce the assembly time for multi-layer, size, and functionality. TSMC claims that its bonding scheme can achieve faster and shorter connections compared to other 3D-IC methods. A report says that Apple will start using TSMC's SoIC technology next year, and AMD will expand its use of this method.
Other Innovations
The implementation of process and packaging technologies has opened the door to a broader range of competitive choices. Unlike the past where the chip roadmap was defined by large chip manufacturers, equipment suppliers, and EDA companies, the world of small chips provides end customers with the tools to make these decisions. This is largely due to the difference in the number of functions that can be placed in a package compared to the number of functions that can be placed within the SoC mask limit. Packages can be horizontally or vertically scaled as needed, and in some cases, they can improve performance through vertical layout planning.
However, given the huge opportunities in the cloud and edge fields (especially with the popularity of artificial intelligence), the three major foundries and their ecosystems are competing to develop new features and capabilities. In some cases, this requires leveraging their existing resources. In other cases, it requires entirely new technologies.
For example, Samsung has begun detailed planning for a custom HBM plan, which includes a 3D DRAM stack with configurable logic layers underneath. This is the second time this approach has been adopted. As early as 2011, Samsung and Micron jointly developed a hybrid memory cube, encapsulating the DRAM stack on top of the logic layer. After JEDEC standardized HBM, HBM won the war, and HMC basically disappeared. But there was nothing wrong with the HMC approach, it was just a matter of timing.
Samsung plans to offer custom HBM as an option in a new form. Memory is one of the key elements that determine performance, and the ability to read and write data between memory and processors faster and move back and forth will have a significant impact on performance and power consumption. If the size of the memory is suitable for a specific workload or data type, and if some processing can be completed within the memory module itself, the amount of data that needs to be moved will be reduced, and these numbers may significantly improve.Figure 7: Samsung Roadmap and Innovation. Source: Semiconductor Engineering/MemCon 2024
In the meantime, Intel has been researching a better way to power densely packed transistors, a problem that has persisted as transistor density and the number of metal layers increase. In the past, power was delivered from the top of the chip downward, but two issues have arisen at the most advanced nodes. One is the challenge of actually providing enough power to each transistor. The other is noise, which can come from the power supply, substrate, or electromagnetic interference. Without proper shielding—due to the thinning of dielectrics and wires, shielding has become increasingly difficult at each new node—noise can affect signal integrity.
Power delivery through the backside of the chip can minimize such issues and reduce line congestion. But this also brings other challenges, such as how to drill holes in thinner substrates without damaging the structure. Intel has apparently solved these problems and plans to launch its PowerVia backside power delivery scheme this year.
TSMC has stated that it plans to achieve backside power delivery with A16 in 2026/2027. Samsung's schedule is roughly the same, implementing backside power delivery in the SF2Z 2nm process.
Intel has also announced plans for a glass substrate, which can provide better planarity and lower defect rates than CMOS. This is particularly important at advanced nodes, as even nanometer-sized pits can cause problems. As with backside power delivery, handling issues are rampant. The advantage is that the thermal expansion coefficient of glass is the same as that of silicon, so it is compatible with the expansion and contraction of silicon components, such as chips. After years of neglect, glass has suddenly become very attractive. In fact, TSMC and Samsung are both researching glass substrates, and the entire industry is starting to design with glass, handle it without breaking, and inspect it.
In the meantime, TSMC places a high value on building an ecosystem and expanding its process offerings. Many industry insiders say that TSMC's real advantage lies in its ability to provide a process development kit for almost any process or package. According to Nikkei News, the foundry produces about 90% of the world's most advanced chips. It also has the most advanced packaging experience, the largest and most extensive ecosystem among all foundries, which is very important.
This ecosystem is crucial. The chip industry is very complex and diverse, and no single company can do everything. The future question is how complete these ecosystems will be, especially if the number of processes continues to grow. For example, EDA suppliers are essential drivers, and any process or packaging method requires automation for the design team to succeed. However, the more processes and packaging options there are, the more difficult it is for EDA suppliers to support every incremental change or improvement, and the lag time between announcements and deliveries may be longer.
ConclusionThe recent supply chain disruptions and geopolitical events have convinced the United States and Europe that they need to repatriate manufacturing and "friendly settle." Investment in semiconductor wafer factories, equipment, tools, and research is unprecedented. The impact on the three major foundries is yet to be seen, but it undoubtedly provides some momentum for new technologies, such as co-packaged optical devices, a large number of new materials, and low-temperature computing.
The impact of all these changes on market share is becoming increasingly difficult to track. It is no longer about which foundry produces chips at the smallest process node, nor even about the number of chips shipped. An advanced package may contain dozens of small chips. The real key is the ability to quickly and efficiently provide significant solutions to customers. In some cases, the driving factor is performance per watt, while in other cases, it may be the time to obtain results, with power consumption being a secondary consideration. There are also cases where it may be that only a leading foundry can provide a sufficient combination of functions. However, it is clear that the competition among foundries is more complex than ever, and the situation is becoming more complex. In this highly complex world, simple comparison indicators are no longer applicable.
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