The importance of mature node chips and processes is increasingly highlighted.
Although all eyes are focused on cutting-edge silicon nodes, many mature nodes still maintain strong production demand.
Starting from the node of about 20nm, subsequent nodes no longer reduce the cost of chips. "In the era of finFET process technology, in order to promote continuous technological progress, the necessary profound process requirements have significantly increased the cost and complexity," explained Andrew Appleby, Chief Product Manager of Logic Library IP at Synopsys Solutions Group. "This has created a strong turning point between each node."
Since then, any reduction in chip size has been accompanied by more expensive processing costs, causing costs to rise sharply. Mask sets are more expensive, and advanced nodes usually require more layers, so they also require more mask sets.
Most foundries and IDMs have strong business on old nodes. David Park, Vice President of Marketing at Tignis, said: "Apart from Intel or memory manufacturers, many IDMs are still producing on nodes of 130nm and above. Some parts simply do not need to be produced on smaller nodes."
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There are also fewer customers for advanced nodes, as not many companies can afford them. Michael Cy Wang, Vice President of Marketing at United Microelectronics Corporation, said: "There are only 2 to 3 customers for the 3nm node. The 7nm node may have 5 to 10 customers. But for the 22 or 28nm nodes, there are dozens, or even more customers."
Target design determines which companies can turn to advanced nodes and which cannot. "The choice of process node depends on the application, and some applications will not turn to nodes that require extreme ultraviolet (EUV) technology in the near future," said Krishna Balachandran, Senior Director of NVM IP Product Management at Synopsys Solutions Division. "This is because a large number of analog circuits cannot benefit from scaling, and do not need to operate at lower power or improve performance. The wafer price of mature nodes is an order of magnitude lower, and the design and mask costs of mature nodes are several orders of magnitude lower."Disruption is the New Normal
Reducing the cost at each node used to be easy. "Historically, even before the 1µm process node, and even the 28nm node, the manufacturing process cost per wafer always increased by about 25% to 30%," says Kevin Lucas, Senior Principal Architect of the Silicon Technology Group at Synopsys. "However, the number of chips per wafer increased by about 50%, so the manufacturing cost per chip at each node decreased by about 20% to 25%." Companies could even take advantage of optical shrink that required almost no engineering work. This was the classic era of Moore's Law, where scaling was prevalent.
At that time, a new node might involve some new process elements, which would add some cost compared to the previous node. But as the number of chips on each wafer increased, the net cost per chip decreased. This situation changed around the 20nm process node. New nodes brought higher performance or lower power consumption, but the cessation of cost reduction meant that moving to the latest node was no longer automatic. "Moving a design to a newer or smaller process node may not produce incremental market value," Park points out.
The discussion about what happens at each node is somewhat vague. Node names are confusing, and companies do not always agree on the "nanometer" level for a given node. Moreover, the numbers assigned to nodes no longer reflect the actual gate length as they used to. Variations such as the use of high-k metal gates have changed the basic comparison point, making larger features behave as if they were smaller. Node naming uses numbers as if some major disruptions had never occurred, and today these names serve no purpose other than as labels for the nodes. In addition, different fabs have made some process changes at different nodes, such as the implementation of finFETs.
The cost increase at new nodes comes from multiple aspects. There may be additional steps (especially in lithography technology), new materials, and there will almost always be new equipment. "Leading fabs will charge a premium because they have to recoup huge capital expenditures and R&D costs," says Wang. "Of course, they need to justify the premium when selling downstream."
One advantage of old processes is the ability to use old equipment. "Many companies are still using equipment from more than 20 years ago to manufacture parts," Park points out. "The factories and equipment have long been depreciated, so they are actually monetizing with each chip they produce."
Tracking Nodes
Silicon processes have evolved from the micrometer scale to the nanometer scale. However, significant process changes have occurred in the last phase of this history. Some of the larger changes include:Between 130nm and 90nm, the wafer size increased from 200 millimeters (8 inches) to 300 millimeters (12 inches). A 300-millimeter wafer is more expensive than a 200-millimeter wafer, but the cost can be spread over more chips, thereby reducing the net chip cost.
At around 45nm, the features are small enough to require computational lithography to push light to print the features clearly.
Around the same time, high-k dielectrics with metal gates began to be used to prevent the gate oxide thickness from becoming too thin.
For 30nm NAND flash memory and 20nm digital logic, due to EUV lithography (13.5nm) not being ready for production, multiple patterning with 193nm immersion technology had to be used. Double patterning (and later quadruple patterning) greatly increased manufacturing costs, but it was the only way to print smaller features.
At the 22nm node, finFETs were first adopted. At the 14nm node, finFETs became mainstream.
EUV was introduced from the 7nm process and became essential at 5nm.
Around 5nm, multiple patterning with EUV began to be used.
The 14-angstrom (Å) node may first start using high numerical aperture (high NA) EUV.
Figure 1: Changes in silicon processing. Larger wafers, high-k metal gates, computational lithography, and multi-patterning have increased processing costs, but they are necessary for performance, power consumption, and (initially) cost. However, around 20 nanometers, chip costs began to increase. Extreme ultraviolet (EUV) and its high numerical aperture (NA) version, as well as gate-all-around (GAA) transistors, are more expensive. (Source: Semiconductor Engineering)Changes in the economic landscape have led to a certain fragmentation in the industry. Some companies and products pursue processes that can offer the highest performance (or lower power consumption) at all times, and their product pricing can support the higher costs at each node. Companies like Intel, Samsung, and Nvidia are in this enviable position. Other companies must stick to older nodes because they cannot set the same prices. Some chips are sold for 20 to 30 cents.
This makes the initiation of designs at certain process nodes (such as 10nm or 7nm) may be reduced, as they are no longer the fastest. But for many ordinary chips being manufactured, they are still too expensive. This means that many designs will pile up on older nodes instead of moving forward. In the meantime, the highest-performing chips will follow the fastest nodes they can reach, leaving a gap on high-performance but outdated nodes.
The production cost of continuous nodes is higher, and the design cost is also higher. "When design companies decide on a process node, they need to consider not only the cost of wafers and masks but also the design cost and its impact on time to market," said Al Blais, head of product management at Synopsys EDA Group. "Process nodes including double patterning require additional design and IP complexity. FinFET designs have additional design restrictions, and EUV does too. High-NA EUV will definitely have new requirements."
Wang from UMC agrees. "Currently, the cost of a set of masks at 5nm or 7nm processes may be between 3 million and 5 million US dollars," he said. "But if you add up all the design engineering and IP costs during the entire project period, the design cost can easily reach tens of millions of US dollars."
Different nodes, different applications
Companies manufacturing cutting-edge chips usually attribute the growth in demand to the growth of AI applications that rely on CPUs, GPUs, or dedicated neural processing chips. Applications that appear less frequently in the headlines include smartphone application processors, high-performance computing (HPC), and cloud server chips.
When the next-generation technology is put into use, the nodes manufacturing these products are the most vulnerable. "Key customers for leading applications are already ready to move to the next cutting-edge node, and then there will be a capacity gap in the wafer factory, especially when the output is high," Wang said.
But more chips are built on older nodes. For example, the demand for power management ICs (PMICs) in electric vehicles is increasing. "PMICs usually use mature nodes such as 180nm or 130nm, but adopt BCD processes (bipolar, CMOS, D-MOS)," Balachandran said. "PMICs are becoming smarter and smarter, integrating more and more digital logic in addition to analog circuits. Therefore, the design is moving towards 90nm, 55nm, and 40nm BCD process nodes."
At the same time, sensors are even more behind the 180nm and 150nm nodes. "For automotive applications that require high voltage resistance, they are integrated with other analog circuits on the BCD process - also mainly using 180nm or 130nm," Balachandran said. "Advanced smart sensors integrate microcontrollers and are moving towards 65nm or 40nm, but this is the latest technology for these applications. Top CMOS image sensors use 22nm low-power processes and are moving towards 12nm finFET processes."Process nodes are typically tailored to specific applications and use cases. "Chips for IoT systems represent some divergence from the target process nodes," says Balachandran. "For cost reasons, most of them stay at nodes like 40nm and 22nm." However, as artificial intelligence moves to the edge, more devices will have some inference capabilities, and the chips that perform this function will require higher performance than other digital logic, so they are turning to 6nm, Balachandran indicates.
Analog and mixed-signal chips also tend to lag behind. Wang of UMC points out: "If the application mixes analog and digital circuits, then we consider 55nm to be the best choice. Pure analog tends to stay at 8-inch advanced nodes—usually 180nm and 150nm."
These old nodes are not static either. Some fabs try to inject new life into old processes by improving them to attract new designs. "As nodes fall from the cutting-edge technology, foundries actively adopt plans to update their mid-range technology products," says Synopsys's Appleby. "This may include introducing specific transistor devices to improve performance or minimize leakage, shrinking processes to improve cost and tool utilization, adding specific RF functions or high voltage for mixed-signal systems, or adding automotive-grade certification."
The emergence of chiplets has also affected these choices. In theory, it is no longer necessary to migrate certain functions to more advanced nodes, just put all functions on one chip. But in fact, only the parts that really need the functions of the advanced nodes can move there, thereby minimizing the chip size of the expensive nodes. The rest can be integrated as separate chiplets within the package.
However, this packaging is currently costly. "It is easy to build chiplets using the process node and technology that best suits each type of chip," Wang says. "If the economic conditions allow, customers will definitely consider turning to chiplets. But the current chiplet solutions still face various yield and cost challenges, and are not cost-effective for many applications." Therefore, although chiplets can save on chip costs, the cost of advanced packaging must be reduced to achieve net cost savings.
Keep the production line running smoothly
While some fabs and foundries focus on breaking through the limits, others (such as UMC) focus on traditional main process nodes. The company considers 22nm or 28nm as its main nodes. "This is the last generation of planar technology," Wang observes. "Switching to finFET will greatly increase manufacturing costs."
In the meantime, some nodes may gradually disappear. "Foundries rarely adopt the 10nm node because the performance does not match the cost," Wang points out. The remaining question is, now that 5, 3, 2nm and below nodes have been introduced, how many new designs will target 7nm. For example, devices that do not require finFET technology will stay at nodes before 14nm or 12nm. EUV is the next major technological breakthrough, which will filter out more designs. Unlike 10nm, 7nm and 5nm may continue to exist, simply because of existing production. But three years later, when these production units are replaced by new node production units, will there be enough new designs to keep the production line running at full capacity? If the main obstacle of finFET is cost, then it seems to be changed to implement continuous process improvement.Conclusion
Given the magnitude of process migration barriers, the design starts between the 12nm and 2nm nodes may decrease compared to the old nodes. For instance, the industry may witness a "snowplow effect" (referring to the concentration of resources, research, or design activities in a specific area or node during the development of technology, due to the breakthrough of some key technologies or nodes, similar to a snowplow pushing snow to one side when clearing snow), where designs accumulate before the 28nm node and forgo the benefits of further leapfrogging due to the lack of significant benefits.
Appleby stated: "Technologies at a sharp turning point, such as the last generation of planar node technology, are destined to have a long lifecycle because they provide the best combination of performance for many product categories that do not require the next generation of nodes."
At the same time, companies using mature technologies are still performing well. "Microchip is a case of a company that is still successfully leveraging old nodes," Park observed. "Last year, they shipped over 8 billion devices from two 8-inch and one 6-inch wafer factories, with process nodes ranging from 0.13µm to 1µm. And they have been profitable every quarter for 32 years. They are just one of the many semiconductor companies that are profitable on old nodes."
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